Each IGBT transistor integrated in a chip of semiconductor material comprises a collector region at a rear surface of the chip, an emitter region at a front surface of the chip opposite the rear surface, an epitaxial region between the emitter region and the collector region, and a gate region in an isolated trench extending into the chip from the front surface (through the emitter region and a part of the epitaxial region).
As should be known, the emitter region comprises a body region formed in the epitaxial region, and two source regions extending from the front surface into the body region along opposite side walls of the trench.
Therefore, each IGBT transistor has a BJT element (defined by the body region, the epitaxial region and the collector region) and a MOSFET element (defined by the source regions, the gate region, the body region and the epitaxial region).
When a driving voltage is applied to the gate region, a channel current flows along the side walls of the trench, between the source region and the epitaxial region (which thus acts as drain region of the MOSFET element). Then, a collector current, amplified by the gain factor of the BJT element with respect to the channel current, flows toward the collector region (so that the epitaxial region also acts as base region of the BJT element connected to the drain region of the MOSFET element).
As combining the properties of high impedance of the gate region of the MOSFET elements and of high collector current of the BJT elements, while requiring reduced area occupation, the IGBT transistors may be used in power applications (for example, for motor control).
In such applications, the IGBT transistors are integrated in large numbers in the chip. In order to achieve high integration density and performance, the IGBT transistors may be arranged in the chip according to suitable configurations. In a typical configuration, the IGBT transistors are arranged in (e.g., strips of) cells, hereinafter active cells, alternating to (e.g., strips of) dummy cells. Each active cell has two gate regions, an emitter region between the gate regions (and comprising two source regions, each one associated to a respective gate region), an epitaxial region and a collector region, whereas each dummy cell comprises two dummy gate regions (and/or a gate region and a dummy gate region, as discussed below), a dummy emitter region between the dummy gate regions, a dummy epitaxial region and a dummy collector region.
The dummy emitter regions are not provided with the source regions, so that the dummy cells do not implement the MOSFET element. As should be known, by properly driving the dummy cells, controlled voltage changes can be induced such as to affect electrical parameters of neighboring active cells (for example, breakdown voltage, gain factor). Thus, such electrical parameters can be controlled downstream of the production process, which gives greater design freedom.
In the state of the art, different solutions for driving the dummy cells exist.
Some solutions provide for connecting the dummy gate regions to the gate regions or the emitter regions, and to leave the dummy emitter regions floating. However, the driving of the dummy gate regions together with the driving of the gate regions (or of the emitter regions) does not provide satisfactory results.
Other solutions provide then to connect the dummy gate regions to each other, and to drive them independently with respect to the gate regions. In such solutions, the dummy emitter regions may be connected to the dummy gate regions, and driven together (or let both floating). Alternatively, as illustrated in U.S. Pat. No. 7,977,704 (the disclosure of which is incorporated by reference), some dummy emitter regions may be connected to the dummy gate regions, and driven independently from the remaining dummy emitter regions.
However, even such solutions do not provide satisfactory results. Indeed, the gate regions of the active cells also identify the dummy gate regions of the dummy cells adjacent thereto. This generates non-optimal biasing of the dummy cells.
These problems are exacerbated in single dummy cell implementations. In such implementations, in fact, each dummy cell is identified by both the gate regions of the active cells adjacent thereto.
Finally, in all the discussed solutions the dummy cells introduce capacitive couplings between the dummy emitter and dummy collector regions and the gate region of the active cells adjacent thereto. Such capacitive couplings determine a reduction of the switching speed of the active cells.